Mechanical stresses within a semiconductor device substrate have been widely used to modulate device performance. For example, in common Si technology, the channel of a transistor is oriented along the {110} planes of silicon. In this arrangement, hole mobility is enhanced when the channel is under compressive stress in the film direction and/or under tensile stress in a direction normal of the channel, while the electron mobility is enhanced when the silicon film is under tensile stress in the film direction and/or under compressive stress in the direction normal of the channel. Therefore, compressive and/or tensile stresses can be advantageously created in the channel regions of a p-channel field effect transistor (pFET) and/or an n-channel field effect transistor (nFET) in order to enhance the performance of such devices.
One possible approach for creating a desirable stressed silicon channel region is to form embedded SiGe or Si:C stressors (i.e., stress wells) at the source and drain regions of a CMOS device to induce compressive or tensile strain in the channel region located between the source and drain regions. Although embedded stressor technology is now well-known, the integration of the embedded stressor into the normal CMOS process flow is extremely challenging. The extent of the performance of the CMOS device depends strongly on the stress generated by the embedded stressor itself, the active dopant concentration in the embedded stressor and the proximity of the embedded stressor to the device channel region.
The importance of overcoming the various deficiencies noted above in embedded stressor technology is evidenced by the extensive technological development directed to this subject material. Some of the more recent advances in this technology can be found, for example, in U.S. Pat. Nos. 6,921,913, 6,831,292, 6,844,227, 6,323,525, and 5,442,205 as well as U.S. Patent Application Publication Nos. 20050082522 and 20040262694 A1.
Despite these advances in the semiconductor industry, further improvement in embedded stressor technology is needed that provides a good balance between stressor proximity and short channels effects. Moreover, an embedded stressor technology is needed that also eliminates possible defect generation, which typically occurs during the ion implantation of deep source/drain regions in prior art embedded stressor technology.